Students and faculty of IIT Madras in collaboration with Semi-conductor Laboratory, Chandigarh developed an in-house and the first microprocessor “SHAKTI” to cater to the increasing demands of high processing power and low power consumption in the robotics, IoT and artificial intelligence applications.
The “SHAKTI” microprocessor is based on the RISC-V architecture which is an open-source architecture. Many companies are adopting RISC-V architecture due to its open-source nature and full control to modify and alter the design as per the specification and requirement.
Recently they successfully tested to run the Linux operating system on the processor which is a huge success as Linux is one of the most popular and secure operating systems which is based on UNIX architecture. Linux OS also powers almost every server in the industry.
They are focused on developing microprocessors which can be used in critical systems, they are planning to design processors for Nuclear reactors, Indian Airforce, Indian Defence systems and other robotics and innovative use cases.
They also developed different variants of microprocessors with specifications which can meet the different processing speed and power requirement based on the application.
C class microcontrollers
- 32-bit 3-8 stage in-order variant aimed at 50-250 Mhz microcontroller variants
- Optional memory protection Very low power static design
- Fault-Tolerant variants for ISO26262 applications
- IoT variants will have compressed/reduced ISA support
I class processors
- 64-bit, 1-4 core, 5-8 stage out of order, aimed at 200-1Ghz industrial control / general purpose applications
- Devices aimed at networking applications will have dual-quad issue support
- Other features – shared L2 cache, AXI bus, threading support
M Class processors
- Enhanced variants of the I-class processors aimed at general-purpose compute, low-end server and mobile applications
- Enhancements over I class – large issue size, quad-threaded, up to 8 cores, freq up to 2.5 GHz, optional NoC fabric
S class processors
- 64-bit superscalar, multi-threaded variant for desktop/server applications.
- 1.2-3Ghz, 2-16 cores, crossbar/ring interconnect, segmented L3 cache
- RapidIO based external cache coherent interconnect for multi-socket applications (up to 256 sockets)
- Hybrid Memory Cube support
- 256/512 bit SIMD
- Specialized variants with FUs for database acceleration, security acceleration.
- Experimental variants will be used as test-bed for our Adaptive System Fabric project which aims to design a data-centre architecture using NV RAM devices and unified interconnects for memory, storage and networking and leverages persistent memory techniques
H class processors
- 64-bit in-order, multi-threaded, HPC variant with 32-100 cores
- 512 bit SIMD
- Interconnect TBD
- Goal is 3-5 + Tflops (DP, sustained)